The IIS Chip Gallery
DIPRO (1989)
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by
| Application | Graphics |
| Technology | 2000 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 5870μm x 3180μm |
| Gates | 1800 |
| Voltage | 5 V |
| Clock | 12 MHz |
The DISplay PROcessor is designed to drive a three digit LED display where each display consists of a matrix of 7x10 points. The chip is desigend to be the central unit for a small card that houses the LED drivers and 8 Bus Latches. This module can further be cascaded to build larger displays of maximum 254 units.In such a cascaded system, commands are transmitted from one module to another using a Centronics RS232 connection.
The system has two RAM banks that houses the display. These can be switched back and forth. It is possible to write directly into the dispolay memory, or completely erase its contents. Further commands allow blinking and shifting of the contents by one pixel.