The IIS Chip Gallery
Autobus (1990)
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by
| Application | Industrial |
| Technology | 1500 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP40 |
| Dimensions | 3090μm x 3090μm |
| Gates | 0 |
| Voltage | 5 V |
| Clock | 0.625 MHz |
AUTOBUS is an integrated sender receiver block. Multiple such blocks are connected using a serial bus. Each AUTOBUS block has an 8-bit identifier which is hardwired. Blocks with the same address can send each other 4-bit data through the serial interface.
In the AUTOBUS system, there are distinct slots for addressing, data transmission and synchronization. A decentralized clocking scheme is used, the synchronization starts with each slot. For the data transfer a Random Access System which was investigated by Peter Mathys. A Collision Resolution Algorithm is used to address problems when two blocks try to send data simultaneaously. In this event, each block waits for a random number of cycles and tries sending again.