The IIS Chip Gallery
ARES (1991)
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by
| Application | Audio |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP40 |
| Dimensions | 6120μm x 3120μm |
| Gates | 9 kGE |
| Voltage | 5 V |
| Clock | 45 MHz |
ARES (A REed Solomon decoder) implements codeing and decoding of (32,28) and (28,24) Reed-Solomon codes as used on the CD system, withthe full capacity to correct up to two errors or four erasures. The core of ARES consists of four parallel GF(2^8) 8x8 bit multipliers implemented using custom layout.
ARES can be used in an experimental setup, combined with a de-interleaving circuit, to directly decode CD signals. It can be used standalone, as error correction system on any channel with little synchronization hardware and some buffering on the receiver side.