Operational amplifiers are a critical element in analog sampled-data circuits, such as SC filters, delta-sigma modulators and pipelined A/D converters. Higher clock frequencies for such circuits translate directly to higher speed requirements for the op-amps. A large unity-gain bandwidth (GBW) is essential for accurate dynamic charge transfer during the short sampling period in SC circuits. This allows to realize high-Q and precise poles, whereas the accurate phase behavior as required for ideal integrators makes 80 dB DC gain, or more, desirable.
In this project an optimal design procedure for folded cascode OTAs has been developed. It is based on an analytical formulation and achieves maximum gain-bandwidth for a given technology and supply current. Regulated-cascode gain enhance 8ment is used to boost the amplifier's total gain to the product of the main and the auxiliary amplifier gain. With this method sufficient DC gain is ensured, even at minimum gate length of the transistors.
To validate the design procedure several OTAs have been implemented, spanning a bias range of 1uA to 10mA. Some OTAs include regulated-cascode gain 1enhancement. All measured GBWs are within 20% of the designed values. The 1 mA-biased OTA consumes 17 mW at 3V and achieves 630 MHz at 51degree phase margin, an excellent performance in its own right.