The IIS Chip Gallery

ItraChip (1998)

by

Markus Thalmann, Manfred Stadler, Thomas Roewer

Main Details

Application	Industrial
Technology	350
Manufacturer	unknown
Type	Research
Package	BGA672
Dimensions	12000μm x 12000μm
Gates	1 MGE
Voltage	2.5 V
Power	3500 mW
Clock	155 MHz

Description

In a research project iof the Integrated Systems Laboratory with Siemens Schweiz AG a complex system on a chip has been developed. The ASIC serves to connect up to 63 useres to the Synchronous Digital Hierarchy (SDH) telecommunication network.

Related Publication

• Markus Thalmann, Manfred Stadler, Thomas Roewer, Norbert Felber, Wolfgang Fichtner, "A single-chip solution for an ADM-1/TMX-1 SDH telecommunication node element", Twelfth Annual IEEE International ASIC/SOC Conference, Sep. 1999, page(s): 147 - 151., DOI: 10.1109/ASIC.1999.806493