The IIS Chip Gallery
Merlin (2000)
| Application | Cryptography |
| Technology | 250 |
| Manufacturer | STM |
| Type | Research |
| Package | LCC68 |
| Dimensions | 1800μm x 1800μm |
| Voltage | 2.5 V |
| Clock | 300 MHz |
For the comparison of common synchronous designs with the new GALS technique, the same function as in the first GALS implementation has been realized in a student design project. The most important parameters to compare were energy consumption, throughput, and silicon area.
Emphasis has therefore been put on a realization that lies as closely as possible to the GALS version. Circuitry from this implementation has then been reused as locally-synchronous islands in the GALS design. Gateable clocks have been implemented for fair energy comparisons.
The chip called MERLIN has been fabricated in 0.25um technology on the same wafer as the GALS version MARILYN. It features a 64-bit datapass controlled by six finite-state machines and with 128 by 16 bits ram. Full testability is ensured by built-in Ram test and full-scan test access. The 2.89 mm2 chip is packaged in a 68-pin chip carrier.
In comparison to this synchronous chip the GALS version saves some 20% energy per encrypted data item at comparable speed. The area consumption of the GALS overhead is 9%.
See also Marilyn the GALS version. More information on GALS can be obtained through our GALS page.