The IIS Chip Gallery
lp8bitADC (2001)
by
| Application | Converter |
| Technology | 250 |
| Manufacturer | STM |
| Type | Research Project |
| Package | LCC44 |
| Dimensions | 2000μm x 1200μm |
| Voltage | 2.5 V |
| Power | 50 mW |
In this project an 8 Bit folding and interpolating analog-todigital converter has been developed. Simultaneous optimization ofall parts ofthe circuit on architectural level results in a converter with 4 parallel folding stages each realizing a folding factor of 8. Additional 8-times interpolation leads to the final resolution of 8 Bit.
The circuit was fabricated in a 0.25 um technology and runs at a single 2.5 V supply. It has a remarkable low power consumption ofonly 50 mW, including the digital decoding logic and the digital output drivers, at a conversion rate of50 MS/s. The measured nonlinearity parameters are INL < 1.25 LSB and DNL < 0.95 LSB. The converter achieves a SNDR of42 dB up to almost Nyquist frequency. This corresponds to an effective resolution of 6.7 Bit. The spurious free dynamic range is higher than 49 dB. The overall chip area is 2.4 mm2.