The IIS Chip Gallery
Eule (2011)
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| Application | Communication |
| Technology | 180 |
| Manufacturer | UMC |
| Type | Semester Thesis |
| Package | QFN56 |
| Dimensions | 1525μm x 1525μm |
| Gates | 60 kGE |
| Voltage | 1.8 V |
| Power | 100 mW, 500MHz |
| Clock | 500 MHz |
This chip implements a soft-output viterbi algorithm for a Turbo decoder. Details to follow soon.