The IIS Chip Gallery

Heartstream (2024)

by

Yichao Zhang, Sergio Mazzola, Marco Bertuletti, Samuel Riedel, Dominic Barthlott

Main Details

Application	Pulp
Technology	12
Manufacturer	GF
Type	Research
Package	QFN56
Dimensions	2500μm x 2000μm
Gates	1
Voltage	0.8 V
Power	10 pW @GHz mW
Clock	720 MHz

Description

Heartstream is a 64-core RISC-V based building block for our Mempool and Terapool based shared-memory architectures that can efficiently scale up to 256/1024 cores.

The MemPool architecture is a flexible and parametric manycore architecture that can scale up to hundreds of individually programmable cores. It utilizes a low-latency L1 scratch pad memory (SPM) which allows 256 independent cores to access a distributed shared L1 memory with low latency. This allows MemPool to scale and efficiently implement a wide range of applications.

Heartstream incorporates two levels of the MemPool hierarchy starting with tiles that combine cores, instruction cache levels, and a subset of shared L1 memory banks connected by a fully connected crossbar. Each tile has remote ports for requesting data from other tiles' SPM and incoming request ports to serve memory requests from remote tiles. Multiple tiles are grouped, and four groups make up the complete Heartstream cluster with interconnected remote interconnects. The design includes additional pipeline stages to minimize latency. The Snitch cores, used as Heartstream's processing elements (PEs), are small 32-bit cores that support the RISC-V RV32IMAFXpulpimg instruction set architecture (ISA). These cores have a pipelined DSP unit that supports Xpulpimg ISA and floating point extensions. The Snitch cores allow for handling multiple outstanding instructions, which helps hide latencies and maintain high throughput.

We have previously published the MemPool architecture:


S. Riedel, M. Cavalcante, R. Andri and L. Benini, "MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory," IEEE Transactions on Computers, vol. 72, no. 12, pp. 3561-3575, 2023, https://doi.org/10.1109/TC.2023.3307796
And have realized a testchip in TSMC65 nm technology called MinPool, which was recently presented at ICECS 2023 in Istanbul.

Heartstream improves on this design in two important aspects

1. FPU support: including FP32, SIMD FP16, and SIMD FP8, which are tuned for communication pipelines with custom instructions for complex operations
2. Systolic computation: architecture with ISA extensions for systolic computation has been shown to improve the performance of data-regular kernels while opening the possibility of creating novel hybrid shared-memory-systolic implementations.

The name of the chip is a bit of a mystery and does not necessarily follow one of the established naming traditions.

This design has been generously supported by the Globalfoundries University Partnership Program.

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