The IIS Chip Gallery
Jass (2024)
by
| Application | Communication |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN40 |
| Dimensions | 2000μm x 2000μm |
| Gates | 2 MGE |
| Voltage | 1.2 V |
| Power | 310 mW @344MHz |
| Clock | 344 MHz |
Jammer-resilient wireless communication systems are urgently needed. While jammer-resilient data detection ASICs like SANDMANand MAED exist, they operate under the assumption that time synchronization has already been established. However, no hardware implementation for jammer-resilient time synchronization exists.
The JASS chip fills this gap: The chip implements the Jammer-Aware SynchroniSation method, which mitigates smart jamming attacks on the synchronization sequence through adaptive spatial filtering. JASS supports a 16-antenna receiver and can mitigate attacks from jammers with up to two antennas and with a jammer signal up to 1,000 times stronger than the synchronization signal. The fabricated 65nm ASIC has a core area of 2.87mm2, consumes a power of 310mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).
The logo depicts a card from Jass, a Swiss card game. The card has been adapted to capture the topic of time synchronization.