| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2235μm x 2235μm |
| Gates | 350 kGE |
| Voltage | 1.2 V |
| Power | 47.4 mW @80 MHz |
| Clock | 80 MHz |
Modern embedded systems often require real-time processing of error-corrected sensor streams. The goal of Crocodilo is to accelerate a computational workload of this kind that consists of three main stages:
First, we have developed a complete software implementation of this workload that can run on the original Croc design (with some minor modifications) and that will serve as a baseline. Then we have improved the original hardware in four main ways:
This project achieved an overall 37x performance speed-up for a real-time signal processing workload on the Croc SoC, reducing total latency from 5.2 ms to 142 us. This result was driven by four targeted hardware enhancements:
The Crocodilo GitHub page contains the entire design.
This chip was designed as part of the VLSI design course at ETH Zurich which uses a (mostly) open source design flow for its exercises. Students are required to modify a Croc based SoC to improve its capabilities somehow to pass the course. This was one of the top-rated designs from the course and has been sent to manufacturing.
Other chips from this series include:
This design has received generous support from Leibniz Institute for High Performance Microelectronics through the BMBF project FMD-QNC (16ME0831).