The IIS Chip Gallery
Pjononcroc (2025)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2235μm x 2235μm |
| Gates | 200 kGE |
| Voltage | 1.2 V |
| Clock | 80 MHz |
PJONonCROC adds a hardware implementation of the single-wire bus protocol "PJDL" to Croc. PJDL is one of the layer 2 options for the open-source PJON network protocol, a multi-master, multi-slave bus protocol designed and implemented in software by Giovanni Blu Mitolo and a whole community of people. PJON and PJDL provide an easy way of connecting many low power and edge devices over a single wire link.
For this project the software implementation of PJDL was complemented with a hardware alternative. With the hardware implementation in PJONonCROC the efficiency of the communication is improved a lot, by moving all the direct sending and receiving tasks from software to hardware. With the implementation of all the receiving logic in hardware, packet loss is also minimized as the hardware can listen on the bus at all times, also when the CPU is busy doing other things. An integrated Direct Memory Access Module (DMA) connected to the PJDL helps to even further take tasks away from the CPU.
The full project can be found on the PJONonCROC GitHub page.
This chip was designed as part of the VLSI design course at ETH Zurich which uses a (mostly) open source design flow for its exercises. Students are required to modify a Croc based SoC to improve its capabilities somehow to pass the course. This was one of the top-rated designs from the course and has been sent to manufacturing.
Other chips from this series include:
This design has received generous support from Leibniz Institute for High Performance Microelectronics through the BMBF project FMD-QNC (16ME0831).