The IIS Chip Gallery
River (2025)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2235μm x 2235μm |
| Gates | 500 kGE |
| Voltage | 1.2 V |
| Power | 76 mW |
| Clock | 80 MHz |
We extended the baseline design by integrating a general-purpose Direct Memory Access (DMA) engine and a Serial Peripheral Interface (SPI) controller to enhance I/O capabilities and support more realistic embedded workloads.
The goal of this project was to extend the Croc SoC with features that enable more realistic and demanding embedded applications. To this end, we implemented two key components: a general- purpose Direct Memory Access (DMA) engine and a Serial Peripheral Interface (SPI) controller. While both modules are useful individually, their integration enables efficient pipelined data processing with minimal CPU involvement.
The DMA engine facilitates autonomous data transfers between memory and peripherals without CPU involvement. This supports two important use cases: (1) streaming input data from peripherals while the CPU concurrently processes earlier data, and (2) overlapping output streaming with computation of the next frame or result. These capabilities significantly improve system throughput. In addition, the DMA outperforms software-based memory copy loops by avoiding CPU overhead.
The SPI peripheral provides a high-speed, full-duplex communication interface to external devices. In contrast to UART, SPI uses a dedicated clock line, allowing for higher data rates and reduced latency. When combined with the DMA engine, SPI enables sustained high-throughput I/O, critical for real-time applications such as digital signal processing, data logging, or streamed computation.
The GitHub repo for the project.
This chip was designed as part of the VLSI design course at ETH Zurich which uses a (mostly) open source design flow for its exercises. Students are required to modify a Croc based SoC to improve its capabilities somehow to pass the course. This was one of the top-rated designs from the course and has been sent to manufacturing.
Other chips from this series include:
This design has received generous support from Leibniz Institute for High Performance Microelectronics through the BMBF project FMD-QNC (16ME0831).