The IIS Chip Gallery
CrocDrive (2026)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2500μm x 2000μm |
| Gates | 180 kGE |
| Voltage | 1.2 V |
| Power | 67.8 mW @100 MHz |
| Clock | 100 MHz |
What does it take to turn a small RISC-V SoC into a real-time motor and power controller without modifying the CPU? CrocDrive extends Croc with AMCP, a memory-mapped hardware peripheral that takes timing-critical PWM generation and quadrature-encoder tracking out of software and handles them autonomously. The CVE2 core is left free to run the control algorithm, while AMCP reuses Croc's existing OBI and GPIO infrastructure. The project was verified from standalone RTL and full-system firmware through closed-loop motor/buck demonstrations, and taken all the way to a timing-clean, LVS-passing physical implementation.
Source, RTL, tests, benchmarks and implementation flow are available at https://github.com/Rishabh-Barola/CrocDrive
This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.