The IIS Chip Gallery
FFTodile (2026)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2500μm x 2000μm |
| Gates | 120 kGE |
| Voltage | 1.2 V |
| Power | 26 mW @100 MHz |
| Clock | 99 MHz |
FFTodile extends the open-source Croc SoC with an FFT accelerator and an I2S receiver for digital MEMS microphones. The system enables real-time audio spectrum analysis while minimizing CPU workload. The accelerator is memory-mapped via OBI, performs 64-point FFTs in 16-bit fixed-point arithmetic, and transfers data directly to and from SRAM. To support audio capture, FFT processing, and program execution simultaneously, the on-chip SRAM was expanded from 4 KB to 16 KB. Implemented in IHP's SG13CMOS5L 130 nm technology, the design achieves a 64-point FFT in approximately 460 clock cycles, around 300 times faster than software execution on the CVE2 core.
The complete source code, documentation, and hardware design are available on GitHub: FFTodile.
This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.