The IIS Chip Gallery
Pulser (2026)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2500μm x 2000μm |
| Gates | 140 kGE |
| Voltage | 1.2 V |
| Power | 30 mW @100 MHz |
| Clock | 100 MHz |
BioPULP Pulser extends the Croc SoC with a programmable multi-channel ultrasound pulser peripheral.
The chip integrates a RISC-V Croc system with on-chip SRAM, standard peripherals, and eight pulse outputs that can generate synchronized dual-frequency excitation, configurable duty cycles, burst lengths, and stop pulses.
The pulser chip was developed by Nico Canzani for embedded ultrasound front-ends, where digital pulse generation combined with an external resonant inductor can reduce the need for bulky high-voltage drive circuitry, later Marc-Andre Wessner updated the SoC and prepared the chip for tapeou.
This chip was originally part of the 2025 edition of the VLSI Design course at ETH Zurich, and was updated by Marc-Andre Wessner which was attending the 2026 edition.