The IIS Chip Gallery

Socc_on_Croc (2026)

by

Mikail Gedik, Thomas Herzog

Main Details

Application	Pulp
Technology	130
Manufacturer	IHP
Type	Teaching
Package	QFN56
Dimensions	2500μm x 2000μm
Gates	0
Voltage	1.2 V
Power	25 mW @100 MHz
Clock	75.525 MHz

Description

The socc on croc peripheral integrates a dedicated VGA text mode display controller operating within the croc domain. The controller is configured for a standard 640x480 resolution at a 60 Hz refresh rate. The rendering pipeline relies on 8x16 pixel bitmap glyph fonts, mapping the screen space into an 80-column by 30-row character array.

The project has two separate GitHub repositories:

• The peripheral is under: https://github.com/mikailgedik/socc_on_croc
• The design flow is under: https://github.com/thomasherzog/socc_on_croc_flow

This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.

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