The IIS Chip Gallery
ChipEES (1987)
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| Application | Test |
| Technology | 3000 |
| Manufacturer | Faselec |
| Type | Semester Thesis |
| Package | DIP40 |
| Dimensions | 3200μm x 2400μm |
| Gates | 400 |
| Voltage | 5 V |
This is a testchip that comprises of six combinational and three sequential circuits. In these circuits, several faults are deliberately integrated. Some of the faults can be programmed (activated) and some are fixed. This chip was specially developed to be used in testing exercises within the IIS.