The IIS Chip Gallery
Scanner (1988)
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| Application | Audio |
| Technology | 2000 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 3200μm x 3200μm |
| Gates | 1 kGE |
This chip failed functional tests, as it uses delay engineering to realize a function. The chip was not simulated for all corners, and the delay assumptions were not met.