The IIS Chip Gallery
Busy_Beaver (1990)
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by
| Application | Fun |
| Technology | 1500 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 3200μm x 3200μm |
| Gates | 2 kGE |
| Voltage | 5 V |
| Clock | 20 MHz |
The Busy Beaver Coprocessor has been designed to solve the Busy Beaver Function for 5 states. This function (also known as the Rado's Sigma Function) is an uncomputable problem from information theory. The input argument is a natural number 'n' that represents the complexity of an algorithm described as a Turing Machine.
This chip can implement 80 million Turing Machine instructions per second and can directly be attached as a co-processor to an existing processor. BBC has one interrupt output and two status registers enabling the chip to be used both with interrupts or by polling.