The IIS Chip Gallery
Quetzalcoatl (1992)
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by
| Application | Graphics |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Research |
| Package | PGA120 |
| Dimensions | 2700μm x 2600μm |
| Gates | 60 kGE |
| Voltage | 5 V |
| Clock | 60 MHz |
Quetzalcoatl is a digital matched filter running at up to 100 MHz, Two realizations of the filter function:
y_{t+1}= x_t - 3 x_{t-2} - 7 x_{t-3} - 9 x_{t-4} - 7 x_{t-5} - 3 x_{t-6} + x_{t-8} differing in their input and output data word widthsand formats have been implemented on a single chip The simpler implementation takes a 1-bit input and provides and 8-bit output in either two's complement or bias-128 format, while themore complex implementation takes a 7-bit input in two's complement or bias-64 format and provides 12-bit output in two's complement or bias-2048 format. Input and output formats may be chosen independently of each other.
The rather short cycle time of 15ns requires special attention to the realization of arithmetic operations, espeically the additions for the 12-bit version. These were implemented using a pipeline of 12-bit carry-save adders.