The IIS Chip Gallery
Lowpass (1994)
by
| Application | Filter |
| Technology | 2000 |
| Manufacturer | Mietec |
| Type | Research Project |
| Package | Unknown |
| Dimensions | 3100μm x 3100μm |
| Voltage | 5 V |
| Clock | 1 MHz |
A wide range of applications, such as modems, vocoders, and video signal processing systems, require linear-phase filters with a steep transition band. Most such filters are either implemented as analog IIR amplitude filters cascaded with IIR delay equalizers, or as digital FIR filters.
The combination of a sigma-delta modulator, a shift register and a switched capacitor (SC) summing circuit represents an alternative way to implement an analog, linear-phase lowpass filter. The sigma-delta modulator is used as front-end to convert the filter input into a binary sequence. The shift register acts as a delay line to hold the binary sequence, whereas the different input capcitors of the SC summer implement the FIR filter coefficients. A low-Q biquad is added to the circuit to improve the stopband attenuation while maintaining the linear-phase behaviour in the passband.
The lowpass filter with a cutoff frequency of 5kHz has been implemented in a 2um BiCMOS technology. The circuit runs at a 1MHz clock an the SC summer consists of 50 input capcaitors. The measured group delay variation in the passband is less than 1us and the measured THD is -80dB for an input sine wave amplitude of 0.7V at 1kHz.
The image quality of the chip photograph is extremely poor. We are working on obtaining a better picture.