The IIS Chip Gallery
SigmaDeltaADC (2000)
by
| Application | Converter |
| Technology | 250 |
| Manufacturer | STM |
| Type | Research Project |
| Dimensions | 1500μm x 1700μm |
| Voltage | 1.2 V |
| Power | 50 mW |
| Clock | 80 MHz |
Analog-to-digital converters with 12 to 13 bit accuracy and 1 MHz signal bandwidth are an important component in both wire-bound and wireless applications such as ADSL or DECT. A 5th order single-loop Sigma Delta modulator for these specifications has been implemented in a 0.25um CMOS technology. The modulator uses a tri-level quantizer to improve stability. At a sampling frequency of 80 MHz, the modulator achieves a dynamic range of 86 dB and a peak SNR of 80 dB over a 1 MHz signal bandwidth with a power consumption of 50 mW.