The IIS Chip Gallery
Seysensational (2010)
by
| Application | Communication |
| Technology | 90 |
| Manufacturer | UMC |
| Type | Semester Thesis |
| Package | PGA120 |
| Dimensions | 3950μm x 1875μm |
| Gates | 600 kGE |
| Voltage | 1.0 V |
| Clock | 360 MHz |
This chip implements Seysen's Lattice Reduction Algorithm for Low-Complexity MIMO Data Detection
In the context of suboptimal MIMO data detection methods, lattice reduction techniques have been proposed recently in order to improve detector performance. For existing hardware implementations, the LLL Algorithm has been considered for this task almost exclusively, whereas the potential of Seysen's lattice reduction algorithm (SA) has only been studied theoretically so far.
In this chip, a hardware implementation of Seysen's algorithm suited to be used in MIMO transceivers has been implemented. It has been shown that several modications to the algorithm can be made in order to decrease hardware-complexity drastically and an architecture which is scaleable in terms of matrix size and throughput constraints has been introduced.