The IIS Chip Gallery
StoneEDGE_B1 (2015)
by
| Application | Communication |
| Technology | 130 |
| Manufacturer | SMIC |
| Type | Research |
| Package | BGA-121 |
| Dimensions | 3700.00μm x 3700.00μm |
| Voltage | 2.8/3.8 V, 1.2V on chip V |
| Clock | 26/83 MHz |
This chip implements a SAW-less -110.5 dBm sensitivity 2G Evolved EDGE physical layer. It includes up/down-conversion, modulation, analog baseband processing, and digital baseband processing. In addition, it includes an autonomous incremental redundancy unit supporting the maximum number of concurrent TFBs, which is 32. Furthermore, the chip supports the highest multislot class 45 and the highest DTM multislot class 44. With this setup it is possible to have a maximum downlink data rate of 592.2 kbps and a maximum uplink data rate of 462.6 kbps. Higher layers can access the chip using an SPI interface whereas the analog outputs can be connected to a power amplifier and an antenna.
The logo on the chip is copyright by Anton Brand and has been used with his permission.
The chip's name stoneEDGE is based on an analogy between the 2G cellular standard enhancement EDGE and a tool from the prehistoric period Stone Age such as an Acheulean. Both are very old yet durable and useful today. This chip is a redesign of an earlier version, hence the name B1.