The IIS Chip Gallery
Maestro (2023)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN64 |
| Dimensions | 4000μm x 3000μm |
| Voltage | 1.2 V |
| Clock | 200 MHz |
Maestro is a highly specialized SoC fabricated in TSMC65 nm that offers a compact and efficient solution for the acceleration of radar and machine learning workloads.
It is composed of two domains: a host and a vector domain. The 32-bit host domain of Maestro is built around a single-core Ibex, while the 64-bit vector domain is Spatz, a tiny vector processor empowered with a tensor unit.
Moreover, a Floating-Point FFT accelerator encapsulated within the vector domain empowers the capabilities of Maestro optimizing the execution of one of the most relevant computation targeting frequency domain applications.
The name of the chip is a tribute to a common slang in Salento ( the southern part of Puglia region in Italy), which is used to address technically competent people. It is also a tribute to a friendship and a common passion for the "La leggenda di Al Jhon and Jack" movie.