The IIS Chip Gallery

Ankara (2024)

by

Can Livanelioglu, Long He, Jiang Gong, Sina Arjmandpour, Gabriele Atzeni, Noah Sassan, Taekwang Jang.

Main Details

Application	Unknown
Technology	22
Manufacturer	GF
Type	Research
Package	Baredie
Dimensions	1800μm x 1600μm
Voltage	0.4 V-1.2V
Power	7.6 mW
Clock	96 MHz in, 4.6GHz out MHz

Description

PLL-XO co-design with a pulse-injection XO driver, achieving 53fs jitter at 4.6GHz and 7.6mW.

Related Publication

• Can Livanelioglu, Long He, Jiang Gong, Sina Arjmandpour, Gabriele Atzeni, Noah Sassan, Taekwang Jang, "A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving 255.2dB FoMJ Including the XO Power and Noise", 2025 IEEE International Solid-State Circuits Conference (ISSCC), DOI: 10.1109/ISSCC49661.2025.10904568