The IIS Chip Gallery
MK2 (2024)
by
| Application | Communication |
| Technology | 22 |
| Manufacturer | GF |
| Type | Research Project |
| Package | baredie |
| Dimensions | 2000μm x 2000μm |
| Gates | 1 |
| Voltage | 0.8 V |
| Clock | 1800 MHz |
This chip is the continuation of the MK1 chip. It includes the PWM block which stimulates the Class-E RF PA. Additionally there is a digital block which implements the storage required to send the modulation data for the transmitter and program the different analog blocks. It is designed to work at 1.8GHz with peak power of 23dBm and a peak power efficiency of 40%.