The IIS Chip Gallery

Picobello (2025)

by

Tim Fischer, Yichao Zhang, Riccardo Fiorani Galotta, Andrea Belano, Marco Bertuletti, Lorenzo Leone, Luca Colagrande, Michael Rogenmoser, Albi Mema, Wu-Young Jang, Cyrill Durrer, Gianluca Bellochi, Yvan Tortorella, Beat Muheim, Zerun Jiang, Davide Rossi, Francesco Conti, Frank K. Gurkaynak, Luca Benini

Main Details

Application	Pulp
Technology	7
Manufacturer	TSMC
Type	Research
Package	PGA84
Dimensions	4766μm x 3911μm
Gates	1000 MGE
Voltage	0.8 V
Power	10 pW @GHz mW
Clock	1000 MHz

Description

Picobello is the latest of our many-core architectures based on the Snitch RV32 core, containing 16 clusters with 9 cores each as well as more than 10Mbyte on-chip memory running at 1GHz fabricated through the TSMC Academic Program supported by Europractice as part of the EU-Pilot project. We expect the chip back in early 2026 and expect to publish results once we have measurement results in place.

Related Publication

No related publications yet