The IIS Chip Gallery
ACDC (2026)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2500μm x 2000μm |
| Gates | 140 kGE |
| Voltage | 1.2 V |
| Power | 25 mW @100 MHz |
| Clock | 100 MHz |
ACDC is an open-source AES-128 accelerator integrated into the Croc SoC. The accelerator computes one 128 bit block in eleven cycles with a round-per-cycle datapath, generates the round keys once and stores them, and exposes both a polled register interface and an autonomous DMA bus master that streams data src dst without further core involvement. The user domain further doubles the on-chip SRAM to 8 KiB and adds a small user ROM.
Compared to a regular SW implementation on the RV32I core, ACDC accelerates AES encryption by about 800 times.
The AES block has been adapted from https://github.com/Rex1110/AES-128 and incorporated into Croc.
This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.