The IIS Chip Gallery

DWorld (2026)

by

Andrea Massimo Rosetti, Lorenzo Matteo Salvatori

Main Details

Application	Pulp
Technology	130
Manufacturer	IHP
Type	Teaching
Package	QFN56
Dimensions	2500μm x 2000μm
Gates	140 kGE
Voltage	1.2 V
Power	37.4 mW @100 MHz
Clock	100 MHz

Description

This project extends the Croc SoC with a custom hardware accelerator that enables high-speed data streaming from external HyperBus memory, offloading these tasks from the core.

The project consists of three main contributions:

• Integration of a parameterizable AXI4-compliant HyperBus controller into the user domain of the Croc SoC, enabling communication with external HyperRAM devices over a low pin-count (12 pins) interface with double data rate (DDR) signaling.
• Implementation of a clock-stop Finite State Machine (FSM) within the HyperBus HY layer that gates the Hyperbus clock during long write transactions to contiguous addresses, effectively performing coalescing.
• Addition of a NeoPixel controller to drive an external 8x8 LED display, offloading the timing-critical WS2812 protocol from software to hardware.

Thanks to these features, our design enables high-throughput data transfer from external memory with minimal core intervention, significantly increasing capacity compared to the baseline Croc chip, effectively opening up a new "DRAM World" (hence the name of our chip) and increasing throughput of memory-bound operations compared to a HyperBus controller without clock-stop functionality.

This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.

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