The IIS Chip Gallery

Fortis (2026)

by

Philipp Kraft, Jeremy Gerster

Main Details

Application	Pulp
Technology	130
Manufacturer	IHP
Type	Teaching
Package	QFN56
Dimensions	2500μm x 2000μm
Gates	120 kGE
Voltage	1.2 V
Power	40 mW @100 MHz
Clock	113.8 MHz

Description

FORTIS is a reliability-oriented extension of the Croc SoC. FORTIS combines a fault-tolerant CVE2 core with a watchdog timer to detect both core faults and system hangs. The core extension adds a boot-time selectable reliable RV32E mode while preserving standard RV32I execution. The watchdog timer monitors software progress and triggers a reset or interrupt when the system stops making progres.

Faults in digital systems caused by radiation, voltage disturbances, or fault-injection attacks can corrupt data or control flow. This can lead to incorrect execution, hangs, or unexpected exceptions. In safety-critical domains, these effects can have severe consequences.

A common technique for improving hardware reliability is spatial redundancy. The hardware is duplicated or triplicated, the redundant instances compute in parallel, and their outputs are compared. While this provides strong protection, it introduces significant overhead in terms of area and power. Especially for smaller systems such as microcontrollers, this may be too expensive.

Microcontrollers often do not require maximum performance, especially when correct execution is more important than execution speed. Many embedded workloads are limited by external events rather than computation. This makes it acceptable to trade execution time for improved reliability. This motivates extending Croc with low-cost reliability mechanisms. Instead of duplicating the entire core, FORTIS reuses the existing 32-register RV32I register file as two RV32E register banks and uses repeated execution to detect faults. A watchdog timer complements this core mechanism by detecting system hangs. Together, these mechanisms provide configurable fault and hang detection with much lower hardware overhead than traditional approaches.

The main contributions of this project are:

• Boot-time selectable RV32I, RV32E, and relRV32E execution modes for the core.
• Reliable RV32E execution by reusing the upper half of the existing register file as redundant state and detecting execution faults through repeated execution.
• Additional shadow registers in the instruction fetch stage.
• A software-configurable watchdog timer to detect hangs.
• Software API for controlling the reliable core and the watchdog timer.
• Build-system support for separate RV32I and RV32E binaries.
• Larger SRAM configuration to support larger software tests and benchmarks.
• Ported RISC-V ISA tests to verify correct core functionality.
• Fault-injection evaluation of the modified core using Synopsys VC Z01X.
• Backend implementation and physical-design evaluation of the modified SoC.

The public GitHub repository of this design can be found under: https://github.com/philipp-kraft/fortis.

This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.

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