The IIS Chip Gallery
Ring_Slink (2026)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2500μm x 2000μm |
| Gates | 200 kGE |
| Voltage | 1.2 V |
| Power | 81.6 mW @80 MHz |
| Clock | 80 MHz |
This project accelerates matrix vector multiplication for machine learning inference on multiple chips using Croc, a lightweight open-source RISC-V SoC. A custom pipelined MAC accelerator using two out of the four SRAM banks for weights and input vector delivering up to a 9.9x speedup on a single chip. Beyond the chip level, multiple Croc instances are coupled via a unidirectional ring bus, distributing large weight matrices across nodes to enable inference on matrices too large for a single chip's memory - reaching speedups of over 60x in the fully distributed configuration.
Access the project database on the following GitHub page.
This chip is part of the 2026 edition of the VLSI Design course at ETH Zurich.