The IIS Chip Gallery
PLL (1990)
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| Application | Industrial |
| Technology | 1500 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 3200μm x 3200μm |
| Gates | 400 |
| Voltage | 5 V |
| Clock | 6.4 MHz |
One of the most critical components in an FM tuner is the local oscillator. High stability and low phase noise are importyant requirements for such a device. The developed chip contains all the components needed for the realization of an FM front end, including a low-noise LC tuned voltage controlled oscillator and a mixer that interfaces directly with a standard 10.7 MHz IF filter.
This mixed analog digital chip is subdivided into two sections. The digital section is standard cell based and contains the frequency dividers and a reference crystal oscillator while the analog one is hand layouted, containing the LC oscillator, the mixer, one divide by 4 prescaler and an opamp for the loop filter.
The technology used is a standard 1.5um double metal CMOS process. Despite its static CMOS design and the 1.5um technology, the prescaler has been demonstrated to run at 320 MHz with low power drain.
The LC tuned VCO requires some external components nut its phase noise, even if slightly higher than that of a good discrete bipolar part, is good enough for this application and compares very favorably with almost any other integrated VCO design.
The PLL can synthesize frequencies between 76.850 MHz and 128 MHz with a resolution of 50 kHz.