The IIS Chip Gallery
LPC (1991)
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| Application | Audio |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 6390μm x 3170μm |
| Gates | 6 kGE |
| Voltage | 5 V |
| Clock | 15 MHz |
This chip implements the LPC (Linear Predictive Coding) algorithm to encode audio data containg speech. It has been shown that this algorithm can achieve compression ratios of 1:20. The system consists of an impuls generator and a noise generator which can selectively be applied to a variable digital filter of 12th order to generate a speech signal. This organization mimics the way humans generate speech.