The IIS Chip Gallery
Video_Controller (1992)
Additional pictures below, click to see larger versions
by
| Application | Graphics |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | PGA124 |
| Dimensions | 3090μm x 6290μm |
| Gates | 5 kGE |
| Voltage | 5 V |
| Clock | 30-55 MHz |
This chip takes a standard video input and converts and is designed to be a part of a system that outputs 24bit 100 Hz output picture. The chip operates on 8-bit values, so three chips operating in a master slave configuration are necessary for the 24-bit picture. The chip consists of two parts that can operate asynchronously each with its own clock frequency. The input part stores the received image and runs at 29.4 MHz. The second part that generates the new Hsync and Vsync signals and sends out the new image has a programmable frequency range between 29.54 and 55.5MHz.