The IIS Chip Gallery
Music (1993)
by
| Application | Processor |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | PGA84 |
| Dimensions | 3100μm x 5400μm |
| Gates | 9 kGE |
| Voltage | 5 V |
| Clock | 66 MHz |
The MUSIC system is a MIMD parallel computer with a peak performance od 3.8 GFLOPS. Each processing element consists of a Motorola 32-bit floating point DSP, memory and an intelligent communication controller. The communication controllers of all processing elements are daisy chained to form a ring.
In each communication cycle, a three dimensional data space is broadcast over the network. Each communication controller may read or write independent subsets of the data space. These subsets, called read and write windows respectively, are computed by the communication controller.
The initial implementation in an FPGA limited the network clock to 8 MHz. The ASIC implementation of the new MUSIC communication controller achieves a netwrok speed of 66 MHz. By doubly pipelining the window generator function the communication bandwidth of the MUSIC system was increased by a factor of eight.
In addition to several graphics modes a new redo function allows to perform a subsequent communication with identical read and write windows. This is especially useful for problems with small and constant data subspaces in which the initialziation of the network outweighs the actual communication.
The name MUSIC stands for MUlti Signal processor with Intelligent Communication. Spaces between pads are occupied with musical terms such as violin, symphony etc..