The IIS Chip Gallery
Morse (1994)
by
| Application | Fun |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP28 |
| Dimensions | 2570μm x 2790μm |
| Gates | 4 kGE |
| Voltage | 5 V |
| Power | 0.23 mW(8 kHz, 5V) |
| Clock | 0.032 MHz |
Decoding manually generated Morse code is arather complicated task becasue the length of the sent signals (dots, dashes and blanks) may vary with thin large ranges. This results in a continous change of the transmission speed often confusing automatic decoders. To cope with such adverse conditions a small neural netwrok solving the problem of fast speed detection was integrated in the ASIC. Measurements and simulations have shown that the chip requires less than ten signals to detect the speed of the sent characters.
The input of the ASIC requires a rectified NF- or digital Hi/Lo signal, which is being filtered on the chip before being fed into the neural network. Any decoded characters are sent directly to the output stage in a specific data format which can directly be displayed on a compact 2 line/16 character LCD module.