The IIS Chip Gallery
ADC3 (1996)
by
| Application | Converter |
| Technology | 1000 |
| Manufacturer | ES2 |
| Type | Research |
| Dimensions | 2281μm x 2257μm |
| Voltage | 5 V |
| Power | 12 mW |
| Clock | 2.6 MHz |
An A/D Converter based on a MOSFET-only current-dividing ladder has been designed. This converter is built entirely of devices available in a standard single-poly digital CMOS process, i.e. without precise passive elements which would require a second poly-silicon layer. The ladder accuracy depends on the matching capability of the MOSFETs which has been proven to be beyond 11 bits in static DAC measurements. The internal signal is a current rather than a voltage due to the output current of the ladder. The circuit consists of the ladder, an input voltage-to-current converter, a current-summing circuit for the ladder output current, a fast comparator, biasing circuitry and the digital successive-approximation register and control. The resolution is 10 bit at a maximum conversion speed of 200kS/s. Measurements show exceptionally good total harmonic distortion values up to 79dB (13bits). The effective number of bits is 9.8 at 10kS/s and 9.4 at 100kS/s. The chip area is 5.2mm^2 and the power consumption is 12mW from a single 5V supply.