The IIS Chip Gallery
TriLevel (1999)
by
| Application | Communication |
| Technology | 250 |
| Manufacturer | STM |
| Type | Research |
| Package | Baredie |
| Dimensions | 1500μm x 750μm |
| Voltage | 2.5 V |
| Power | 50 mW |
Analog-to-digital converters with 12- to 13-bit accuracy and 1 MHz signal bandwidth are an important component in both wire-bound and wireless communication applications, such as ADSL modems and DECT cordless telephones. Although both pipelined and oversampled sigma-delta A/D converters have proven to be capable of such bandwidth-accuracy combination in recent years, oversampled converters have the advantage of not requiring a precision sample-and-hold circuit and of significantly relaxed specifications for the anti-aliasing filter.
A 5th-order single-loop sigma-delta modulator has been implemented in a 0.25 mm digital CMOS process (Philips C050) with a supply voltage of only 2.5 V and without capacitor option. A tri-level quantizer is used to improve loop stability. The sampling frequency of the modulator is 80 MHz and the oversampling ratio is 32. Measured over a 1 MHz signal bandwidth, dynamic range is 86 dB, peak SNR is 80 dB and peak SNDR is 78 dB. The modulator consumes 50 mW. The chip area is 1.1 mm2.