The IIS Chip Gallery
Zathras (1999)
by
| Application | Graphics |
| Technology | 350 |
| Manufacturer | austriamicrosystems |
| Type | Research |
| Package | PGA100 |
| Dimensions | 3500μm x 3500μm |
| Voltage | 3 V |
| Power | 100 mW |
| Clock | 200 MHz |
For the miniaturized high-resolution CCD camera a chip set has been developed by the Integrated Systems Laboratory. ZATHRAS is one of the ASICs for the camera head. It contains a clock receiver, a CCD pulse generator, a parameter link interface, and a high-speed image data transmitter.
The ZATHRAS ASIC is a configurable, fully digital pulse generator with an on-chip 400 Mbit/s image data transmitter for use with a Kodak KAI-1010 series CCD image sensor and two CCD signal digitizers (either Burr-Brown VSP2101, Exar XRD98L60 or Analog Devices AD9803). Through the additional off-chip driver stages, the ASIC supplies the signals required for correct operation of the sensor. Furthermore ZATHRAS generates all necessary control signals for the CCD signal digitizers. Over a parameter link all registers of the camera head can be configured and the auto focus can be actively controlled.