The IIS Chip Gallery

Silverbird (2000)

by

Peter Luethi, Stefan Moscibroda, Daniel Forrer, Thomas Roewer, Manfred Stadler

Main Details

Application	Processor
Technology	600
Manufacturer	austriamicrosystems
Type	Semester Thesis
Package	PGA120
Dimensions	4600μm x 4600μm
Gates	25 kGE
Voltage	5 V
Clock	118.6 MHz

Description

The result of this semester thesis is an IP module or a virtual component (VC) of a RISC processor core. It realizes a Harvard architecture with a four-stage pipeline and delayed branch instructions. The register bank of the processor is implemented as top-ofstack which results in very efficient interrupt handling capability.

The source of the processor in hardware-description language (VHDL) enables the designer, who wants to use this VC, to parametrize it in stack and memory width as well as in the RISC instruction set. The less instructions are selected, the lower the amount of silicon will be after synthesis.

The virtual component has been integrated to verify the concept. Key specifications and parameter set of the student chip called SILVERBIRD are:

• 0.6um 3 metal layer CMOS process AMS HK3.20
• 4.6 by 4.6 mm2 die, 3.6 by 3.6 mm2 core size
• 105,000 transistors (inc. RAM), 8712 standardcells
• 100 MIPS @ 100 MHz clock frequency.
• 2 clock cycles interrupt latency
• Instruction address / data width 11 / 16 bit
• Data memory address width 10 bit
• Number of data / address registers 12 / 4
• Stack / return address stack depth 4 / 20
• On-chip data memory (SRAM) 1K x 16 bit
Peter Luethi has a www page on Silverbird, which contains much more information on this chip.

Related Publication

• Peter Luethi, Thomas Roewer, Manfred Stadler, Daniel Forrer, Stefan Moscibroda, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A parametrizable hybrid stack-register processor as soft intellectual property module", 13th Annual IEEE International ASIC/SOC Conference, 2000, page(s): 87 - 91, DOI: 10.1109/ASIC.2000.880681