|Dimensions||1900μm x 1200μm|
This chip is a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8- m BiCMOS technology. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.