The IIS Chip Gallery

TripleB (2003)

by

Reinhard Bischoff, Jonas Biveroni, Markus Bruehwiler, Andreas Burg, David Perels

Main Details

Application	Processor
Technology	250
Manufacturer	UMC
Type	Semester Thesis
Package	LCC84
Dimensions	2500μm x 2500μm
Gates	14 kGE
Voltage	2.5 V
Clock	160 MHz

Description

This chip is a dedicated processor for generating pseudo random sequences and structured binary codes for communication systems. It consists of four parallel bit ALUs for simple boolean operations on individual bits, and a word ALU that supports a basic instruction set similar to conventional processors.

Related Publication

• David Perels, Reinhard Bischoff, Jonas Biveroni, Markus Bruehwiler, Andreas Burg, Norbert Felber, Wolfgang Fichtner, "Programmable Code Generator for Software Defined Radio", In Proc. of 35th Asilomar Conference on signals, Systems and Computers, 2003., DOI: 10.1109/ACSSC.2003.1292362