Andreas Burg

Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006.

In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was a visiting researcher with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. Since January 2009, he is an Assistant Professor at the ETH Zurich and Head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory of the ETH Zurich. In his professional career, Mr. Burg was involved in the development of more than 20 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP).

In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, Dr. Burg was awarded a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship at ETH.

Research interests and expertise

• Circuits and systems for telecommunications (wireless and wired)
• Prototyping and silicon implementation of new communication technologies
• Development of communication algorithms and optimization for hardware implementation
• Low-power VLSI signal processing for communications and other applications
• Digital integrated circuits
• Circuits for image and video processing

Designer for following chips

• 3d_dct (1998)
• Scanconverter (1999)
• 3d_dct (2000)
• 2d_dct (2001)
• Aac (2001)
• Fastcore (2003)
• Stereopsis (2003)
• Transparent_ide (2003)
• Tripleb (2003)
• Qr_preamp (2004)
• Sphere (2004)
• Viterbi (2004)
• Fingermouse (2005)
• Mimo_ofdm (2005)
• Ldpc_decoder (2006)
• Maxlogmap (2006)
• Pipenet (2007)
• Semic (2007)
• Svd_devaanoom (2007)
• Edge_receiver (2008)
• Frog (2008)
• Clsn601p (2008)
• Dicle (2009)
• Matterhorn (2009)
• Firat (2010)
• Pulpv3 (2015)
• Rosetta (2019)

Publications related to the chips in the gallery

• Guiseppe Acunto, Miquel Sans, Andreas Burg, Wolfgang Fichtner, "An ASIC implementation of the Adaptive Arithmetic Coding", 26th Asilomar Conference on Signals, Systems and Computers, USA
  
  
• Frank K. Gurkaynak, Andreas Burg, Dominique Gasser, Franco Hug, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A 2Gb/s Balanced AES Crypto-Chip Implementation", 14th ACM Great Lakes VLSI Symposium, GLSVLSI 2004, DOI: 10.1145/988952.988963
  
  
• Michael Kuhn, Stephan Moser, Oliver Isler, Frank K. Gurkaynak, Andreas Burg, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Efficient ASIC implementation of a real-time depth mapping stereo vision system", IEEE Midwestern Symposium on Circuits and Systems MWSCAS 2003
  
  
• David Perels, Reinhard Bischoff, Jonas Biveroni, Markus Bruehwiler, Andreas Burg, Norbert Felber, Wolfgang Fichtner, "Programmable Code Generator for Software Defined Radio", In Proc. of 35th Asilomar Conference on signals, Systems and Computers, 2003., DOI: 10.1109/ACSSC.2003.1292362
  
  
• Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger, Wolfgang Fichtner, Helmut Boelcskei, "VLSI implementation of MIMO detection using the sphere decoding algorithm", IEEE Journal of Solid-State Circuits, Volume: 40 , Issue: 7, Year: 2005 , Page(s): 1566 - 1577, DOI: 10.1109/JSSC.2005.847505
  
  
• David Perels, Simon Haene, Peter Luethi, Andreas Burg, Wolfgang Fichtner, Helmut Boelcskei, "ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs", Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Page(s): 215 - 218, DOI: 10.1109/ESSCIR.2005.1541598
  
  
• Simon Haene, Andreas Burg, Norbert Felber, Wolfgang Fichtner, "OFDM channel estimation algorithm and ASIC implementation", 4th European Conference on Circuits and Systems for Communications, ECCSC 2008, Page(s): 270 - 275, DOI: 10.1109/ECCSC.2008.4611691
  
  
• Davide Cescato, Moritz Borgmann, Helmut Boelcskei, Jan Hansen, Andreas Burg, "Interpolation-based QR decomposition in MIMO-OFDM systems", Proc. of IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications (SPAWC), New York, NY, USA, pp. 945-949, June 2005, DOI: 10.1109/SPAWC.2005.1506279
  
  
• Peter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner, "VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition", IEEE International Symposium on Circuits and Systems, ISCAS 2007, Page(s): 1421 - 1424, DOI: 10.1109/ISCAS.2007.378495
  
  
• Christoph Studer, Patrick Bloesch, Peter Friedli, Andreas Burg, "Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs", Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, 2007, Page(s): 1986 - 1990., DOI: 10.1109/ACSSC.2007.4487584
  
  
• Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang, "Design and Optimization of an HSDPA Turbo Decoder ASIC", IEEE Journal of Solid-State Circuits, Vol: 44, Issue: 1 ,2009 , Page(s): 98 - 106, DOI: 10.1109/JSSC.2008.2007166
  
  
• Stefan Eberli, Andreas Burg, Wolfgang Fichtner, "Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor", Microelectronics Journal, Vol: 40, Issue 11, Nov. 2009, Pages: 1642-1649, DOI: 10.1016/j.mejo.2009.02.005
  
  
• Christoph Studer, Nicholas Preyss, Christoph Roth, Andreas Burg, "Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes", 42nd Asilomar Conference on Signals, Systems and Computers, 2008, Page(s): 1137 - 1142, DOI: 10.1109/ACSSC.2008.5074592
  
  
• Lukas Bruderer, Christoph Studer, Markus Wenk, Dominik Seethaler, Andreas Burg, "VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp: 3745 - 3748, DOI: 10.1109/ISCAS.2010.5537742
  
  
• Andreas Burg, Simon Haene, Moritz Borgmann, Daniel Baum, Thomas Thaler, Flavio Carbognani, Stefan Zwicky, Luis Barbero, Christian Senning, Pierre Greisen, Thomas Peter, Claudio Foelmli, Pedro Tejera, Ulrich Schuster, Andy Staudacher, "A 4-stream 802.11n baseband transceiver in 0.13um CMOS", Symposium on VLSI Circuits, 16-18 June 2009, page(s): 282 - 283, Kyoto, Japan
  
  
• Christoph Roth, Pascal Meinerzhagen, Christoph Studer, Andreas Burg, "A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS", 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), DOI: 10.1109/ASSCC.2010.5716618
  
  
• Patrick Maechler, Pierre Greisen, Norbert Felber, Andreas Burg, "Matching pursuit: Evaluation and implementatio for LTE channel estimation", IEEE International Symposium on Circuits and Systems (ISCAS 2010), pp 589-592, DOI: 10.1109/ISCAS.2010.5537528
  
  
• Alessandro Cevrero, Yusuf Leblebici, Paolo Ienne, Andreas Burg, "A 5.35 mm2 10GBASE-T Ethernet LDPC decoder chip in 90 nm CMOS", 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), DOI: 10.1109/ASSCC.2010.5716619
  
  
• Patrick Maechler, Benjamin Sporrer, Sebastian Steiner, Norbert Felber, Andreas Burg, "Implementation of greedy algorithms for LTE sparse channel estimation", Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR 2010), pp 400-405, DOI: 10.1109/ACSSC.2010.5757587
  
  
• Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus Gross, "Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications", IEEE Transactions on Circuits and Systems for Video Technology, vol:22, Issue:11, pp:1577-1589, DOI: 10.1109/TCSVT.2012.2201671
  
  
• Patrick Maechler, Christoph Studer, David Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard Baraniuk, "VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol:2, issue:3, pp 579-590, DOI: 10.1109/JETCAS.2012.2214636
  
  
• Harald Kroell, Stefan Zwicky, Benjamin Weber, Christoph Roth, David Tschopp, Christian Benkeser, Andreas Burg, Qiuting Huang, "An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity", IEEE Journal of Solid State Circuits, vol 50, no 7, pp1690-1701, DOI: 10.1109/JSSC.2015.2417802
  
  
• Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beigne, Fabien Clermidy, Philippe Flatresse, Luca Benini, "Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster", IEEE Micro, vol. 37, no. 5, pp. 20-31, DOI: 10.1109/MM.2017.3711645
  
  
• Davide Rossi, Antonio Pullini, Christoph Mueller, Igor Loi, Francesco Conti, Andreas Burg, Luca Benini, Philippe Flatresse, "A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors", IEEE Design & Test, vol. 34, no. 6, pp. 46-53, Dec. 2017, DOI: 10.1109/MDAT.2017.2750907
  
  
• Odem Harel, Emanuel Nieto Casarrubias, Manuel Eggimann, Frank K. Gurkaynak, Luca Benini, Adam Teman, Robert Gitermann, Andreas Burg, "64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique", in IEEE Solid-State Circuits Letters, vol. 5, pp. 170-173, 2022, DOI: 10.1109/LSSC.2022.3182531