The IIS Chip Gallery
ADC (2006)
by
| Application | Converter |
| Technology | 130 |
| Manufacturer | STM |
| Type | Research |
| Package | Baredie |
| Dimensions | 1440μm x 950μm |
| Voltage | 1.2 V |
| Power | 20.5 mW |
Wireless communication has seen a tremendous growth in past decades. Different coexisting standards have proliferated covering wide, local and personal area networks, cellular standards such as GSM and UMTS as well as standards for local environment such as the WLAN family. From the user's point of view, the current trends call for designs that allow convergence of wireless services, allowing access to different standards from the same wireless device and cost effective solutions for intercontinental roaming.
As advances in technology provide increasingly faster and less expensive digital hardware, expensive analog tuners and filters of radio receivers will be replaced with digital hardware. Trends in receiver design have evolved this goal by incorporating digitization closer and closer to the receive antenna. The A/D converter in the receive path has therefore become one of the key elements in such a device.
An attractive converter architecture for such a multi-standard receiver is the SD converter, since speed can be traded for resolution. Nevertheless, covering multiple cellular and WLAN standards is a challenge, because the spread of bandwidth and resolution between the different standards is very high.
In this project, a switched-capacitor multi-standard DS modulator in 2-2 cascade has been realized in standard 0.13 mm CMOS. The modulator achieves 88 dB dynamic range in EDGE, 79 dB in UMTS and 67 dB in WLAN mode. High linearity, reaching -92dB THD and 34 dBm iIP3 for EDGE, makes it most suitable for wireless. The modulator covers 0.1 to 10 MHz signal bandwidth with a corresponding power consumption between 2.9 and 20.5 mW from 1.2 V.