|Dimensions||2500μm x 500μm|
|Power||0.0114 mW, 106kHz|
Radio Frequency Identification (RFID) technology is currently revolutionizing supply chain management. Cloning-resistant RFID tags could put a permanent stop to product piracy. Tag authentication based on Elliptic Curve Cryptography (ECC), a sound and standardized cryptographic methodology, will provide this copy-protection facility.
The small key sizes achievable with ECC render it the only public-key cryptosystem viable for an RFID application. This work presents a new approach for ECC on devices with a fiercely constrained die-area and power budget. It employs a data path with a word size of 16 bits. A design-space exploration of word-level algorithms led to the development of a new multiplication with interleaved modular reduction method. Minor modifications to a multiply-accumulate (MAC) unit led to a hardware component capable to implement this and all other algorithms required for the elliptic-curve point multiplication most efficiently. The point multiplication is the operation that lends security to ECC-based cryptographic primitives like authentication. The ECCon ASIC designed and fabricated as part of this thesis is rounded off by an ISO-18000-3-1 compliant digital RFID frontend augmented with the capability to perform a restricted version of the elliptic curve digital signature algorithm (ECDSA). Special attention was paid to the possibility of side-channel attacks and measures were implemented to provide high resilience against them. The ECCon processor was fabricated using the UMC 180 nm CMOS technology. The area it requires equals to 3,685 gate equivalents. It performs an elliptic curve point multiplication in 306,587 clock cycles and has a power consumption of 11.4 mW at a clock frequency of 106 kHz)
This chip is one of the long series of ASICs that was manufactured in collaboration with the IAIK of TU-Graz.