|Dimensions||1875μm x 1875μm|
In this Master Thesis, an ASIC had to be developed which serves to treat audio recordings with extremely long acoustic room responses. Both the computational effort, and the storage requirements for the room response and the audio sequence to be processed, are very large. Algorithms had to be found to reduce the memory interface bandwidth and the number of required multipliers to a manageable amount. The new algorithm makes use of the redundancy in consecutive output samples in order to lower the memory throughput. After simulation and optimization of this algorithm, it was implemented in VHDL with the constraint for the layout to fit on the available silicon area for student designs (90 nm Mini@sic Europractice Multi Project Wafer). The resulting ASIC, connected to an external SRAM, is able to handle an impulse response of 87,300 samples at 48 kHz, corresponding to 1.8 seconds reverberation. A solution was found which allows to multiply this duration by the number of chips connected in a cascade. The latency of the resulting audio stream could be kept as low as 37.5 ms, which enables real-time applications. The chip features a time-domainmultiplexed standard audio interface to be connected to common Digital Signal Processors and audio AD and DA converters. It operates with 10 multipliers at a clock frequency of 245.76 MHz. Audio and impulse response data are 24 bit PCM. The ASIC in UMC L90 CMOS technology has a die area of 1.7 mm by 1.7 mm and 56 pins.