The IIS Chip Gallery

Turbo_Butterfly (2010)

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by

Felix Arnold, Michael Jakob, Daniel Stadelmann, Kristoffer Nordstroem, Christian Benkeser, Christoph Roth, Lukas Bruderer

Main Details

Application	Communication
Technology	180
Manufacturer	UMC
Type	Semester Thesis
Package	QFN56
Dimensions	1525μm x 1525μm
Gates	80 kGE
Voltage	1.8 V
Clock	100 MHz

Description

Viterbi Decoder Implementation for Evolved EDGE

This chip contains a version of LaLe and therefore also a Turbo Decoder. Originally the chip was named just Butterfly referring to the butterfly structure of a classical Viterbi structure. After the Turbo core was added, it was upgraded to Turbo Butterfly.

Related Publication

• Christian Benkeser, Christoph Roth, Qiuting Huang, "Turbo decoder design for high code rates", IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC 2012), pp 71-75, DOI: 10.1109/VLSI-SoC.2012.6379008