The IIS Chip Gallery
Camp (2012)
Additional pictures below, click to see larger versions
by
| Application | Audio |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN56 |
| Dimensions | 1920μm x 1920μm |
| Gates | 500 kGE |
| Voltage | 1.2 V |
| Power | 1 mW |
| Clock | 293 MHz |
This is our first TSMC-65 chip. It was mainly designed to see the design flow for this technology. The vehicle is an implementation of the de-clicking algorithm which uses compressed sensing techniques to remove noise from audio recordings. This chip is a continuation of the chip AMP that was produced earlier. It has two independent cores in it.
There was a very interesting problem with this chip. During the later phases of the design, we wanted to see if the post-layout simulation worked correctly. The simulation gave a problem. We thought that the problem was with the SDF backannotation. it turns out that, due to an error, the SDF backannotation was not made at all. Still, somehow earlier versions of the design seemed to bring correct results. The problem in the SDF backannotation was that there were empty TIMINGCHECK statements in the SDF file. According to the SDF description "any number of timing check definitions may appear..". Modelsim responded with an ERROR when there were no TIMINGCHECK statements, that is why the SDF read in failed. Further investigation revealed that the reason for the empty TIMINGCHECK statements was that the timing libraries for 8 RAMS were not read in correctly. Thus they had no timing information. Not only did this affect the SDF, but the normal timing optimization suffered as well. Once the correct timing libraries were read in the design had a slack of -1.5ns at a clock period of 3.5ns.
The problem is interesting because a chain of mistakes resulted in the discovery: If the simulation (somehow) ran without problems the last time or if Modelsim had not complained about missing TIMINGCHECK statements with an ERROR, we would not have discovered this problem. The result would have been a circuit that works about 40% slower, even though all post-layout timing checks and post-layout simulations suggested otherwise. This shows how delicate the entire business is, and how easily things can be missed